Typically, an SRAM cell includes a pair of inverters with the outputs of the inverters cross-coupled to form a flip-flop. The typical SRAM cell includes four transistors for storing data and two transistors for selection of a particular cell. Unlike dynamic random access memory (DRAM) cells, because of the flip-flop feedback effect, SRAM cells typically enable storage of static data even without refresh operations.
FIG. 1 is a circuit diagram of a conventional SRAM cell. Referring to FIG. 1, an SRAM cell includes a pair of access transistors AT1 and AT2, a pair of pull-up transistors PT1 and PT2, and a pair of driver transistors DT1 and DT2. The transistors PT1 and DT1 constitute a first inverter, and the transistors PT2 and DT2 constitute a second inverter. The first and second inverters are cross-coupled at nodes N1 and N2.
Source regions of the transistors DT1 and DT2 are coupled to a ground line Vss, and source regions of the transistors PT1 and PT2 are coupled to a power line Vdd. A drain region of the transistor AT1 is coupled to a first bit line BL1, and a drain region of the transistor AT2 is coupled to a second bit line BL2. Source regions of the transistors AT1 and AT2 are coupled to nodes N1 and N2, respectively. Gate electrodes of the transistors AT1 and AT2 are coupled to a common word line WL.
FIG. 2 is a top plan view of a conventional SRAM cell. As seen in FIG. 2, a field region 210 is formed at a substrate to define first and second active regions 200a and 200b. An N+ n-type active region is formed by heavily doping n-type impurities into a region denoted by “A”, and a P+ p-type active region is formed by heavily doping p-type impurities into a region denoted by “B”.
The word line 220 crosses over the active region 200a to form gates of the transistors AT1 and AT2. A first gate electrode 230a is disposed at right angles to the word line 220, and crosses over the active regions 200a and 200b to form gates of the transistors DT1 and PT1 and to connect the gates. A second gate electrode 230b is disposed in parallel with the first gate electrode 230a, that form gates of the transistors DT2 and PT2, and connects the gates.
The n-type impurity region N+ disposed between the transistors AT1 and DT1 becomes the node N1. The node N1 is coupled to a local interconnection line (not shown) through a contact CT2a. The local interconnection line is coupled to a drain of the transistor PT1 through a contact CT5a, and coupled to the gates of the transistors DT2 and PT2.
The n-type impurity region N+ disposed between the transistors AT2 and DT2 becomes the node N2. The node N2 is coupled to the local interconnection line (not shown) through a contact CT2b. The local interconnection line is coupled to a drain of the transistor PT2 through a contact CT5b, and coupled to the gates of the transistors DT1 and PT1.
The contacts CT1a and CT1b connect the drains of the transistors AT1 and AT2 to the separate bit lines (not shown), respectively. The contact CT4 connects the source of the transistors PT1 and PT2 to the power line Vdd (not shown), and the contact CT6 connects the source of the transistors DT1 and DT2 to a ground line Vss (not shown).
As semiconductor integrated circuits have become more highly integrated and operate at higher speed with lower power, extensive techniques for forming SOI devices have been investigated. SOI typically includes forming a single crystal silicon layer on an insulation layer to enable integration of devices disposed on the silicon layer.
FIG. 3 is a cross-sectional view of a conventional transistor formed on a SOI substrate. Referring to FIG. 3, a buried insulation layer 305 is formed on a base substrate 300 and a p-type lightly doped semiconductor layer is formed on the buried insulation layer 305. A field region 310 is formed at the semiconductor layer to define an active region. Source and drain regions 315 are provided in the semiconductor layer. A body 320 is provided between the source and drain regions 315. A gate electrode 330 is formed on the body 320, and a gate insulation layer 325 is provided between the gate electrode 330 and the body 320. Gate spacers 335 are formed on sidewalls of the gate electrode 330.
As compared with semiconductor devices fabricated using conventional bulk wafers, SOI devices fabricated using SOI wafers may have advantages for high-speed operations due to a low junction capacitance, reduction in soft errors caused by a α-particle in memory devices, and the like.
However, conventional SOI devices may suffer from floating body effects. Floating body effect may arise when the body of the device is not connected to a fixed electric potential, the body of the device has an electric potential based on its history. For example, when both source and drain regions of the transistor are at a high logic level, the body region is charged with equivalent voltages. Thereafter, when the source (or the drain) of the transistor changes quickly to a low logic level, the junction between the source (or the drain) and the body region is positively biased. As a result, a parasitic bipolar transistor may be formed that can lead to the generation of a leakage current.
FIGS. 4A and 4B illustrate that a bipolar transistor may operate to generate a leakage current in a MOS transistor.
Referring to FIG. 4A, even if an access transistor is in the off-state, a leakage current may be generated due to floating body effect. For example, when a high signal is stored in a node, the bit line voltage may be applied at the high level for a time of approximately 1 μs to 100 ms. Thereafter, the bit line voltage is changed to a low level for a short time of approximately 1 to 10 ns. In this case, a leakage current is generated at the node toward the bit line.
Referring to FIG. 4B, a graph represents leakage current as a function of operating voltage of the bit line utilizing a length of the gate electrode of 0.11 μm, an operating voltage of the bit line was applied at a high level for a time of approximately 10 ms. Thereafter, the operating voltage of the bit line was applied at a low level for a time of 5 ns. As a result, a leakage current was generated.